On the Effectiveness of the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture

In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through a scheduling algorithm that can be implemented in hardware. These VLIW instructions are cached so that the machine can spend most of its time executing VLIW instructions without sacrificing any binary compatibility. This paper evaluates the effectiveness of the DTSVLIW instruction-scheduling algorithm by comparing it with the first come first served (FCFS) algorithm, used for microinstruction compaction, and the Greedy algorithm, used by the Dynamic Instruction Formatting architecture. In order to perform these comparisons, we have performed experiments using the SPECint95 benchmark suite. KeywordsVLIW, instruction scheduling, ILP